--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   22:36:10 08/13/2015
-- Design Name:   
-- Module Name:   G:/fpga_test/test_freq_cnter_dtime.vhd
-- Project Name:  fpga_test
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: frequence_counter
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY test_freq_cnter_dtime IS
END test_freq_cnter_dtime;
 
ARCHITECTURE behavior OF test_freq_cnter_dtime IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT frequence_counter
    PORT(
         hclk : IN  std_logic;counter_clk_out : out std_logic;
			clr : IN std_logic;
			md : in  STD_LOGIC_VECTOR (1 downto 0);
			test_cnt_out : out STD_LOGIC_VECTOR (7 downto 0);
         rd_clk : OUT  std_logic;
         rd_en : IN  std_logic;
         fin_x : IN  std_logic;
         fin_y : IN  std_logic;
         dout_0 : OUT  std_logic;
         dout_x : OUT  std_logic;
         dout_y : OUT  std_logic;
         ready : OUT  std_logic;
			test_in: IN std_logic;
			test_out: OUT std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal hclk : std_logic := '0';
	signal clr : std_logic := '1';
	signal md : std_logic_vector(1 downto 0) := "00";
   signal rd_clk : std_logic := '0';
   signal rd_en : std_logic := '0';
   signal fin_x : std_logic := '0';
   signal fin_y : std_logic := '0';
	signal test_in : std_logic := '0';

 	--Outputs
   signal dout_0 : std_logic;signal counter_clk_out : std_logic;
   signal dout_x : std_logic;
   signal dout_y : std_logic;
   signal ready : std_logic;
	signal test_out : STD_LOGIC := '0';
	signal test_cnt_out : STD_LOGIC_VECTOR (7 downto 0) := (others=>'0');

   -- Clock period definitions
   constant hclk_period : time := 5 ns;
   constant fin_period : time := 50 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: frequence_counter PORT MAP (
          hclk => hclk,counter_clk_out=>counter_clk_out,
			 clr => clr,
			 md => md,
			 test_cnt_out => test_cnt_out,
          rd_clk => rd_clk,
          rd_en => rd_en,
          fin_x => fin_x,
          fin_y => fin_y,
          dout_0 => dout_0,
          dout_x => dout_x,
          dout_y => dout_y,
          ready => ready,
			 test_in=> test_in,
			 test_out=> test_out
        );

   -- Clock process definitions
   hclk_process :process
   begin
		hclk <= '0';
		wait for hclk_period/2;
		hclk <= '1';
		wait for hclk_period/2;
   end process;
 
   finx_process :process
   begin
		fin_x <= '0';
		wait for fin_period/5 * 2;
		fin_x <= '1';
		wait for fin_period/5 * 3;
   end process;
 
   finy_process :process
   begin
		wait for fin_period/5;
		fin_y <= '1';
		wait for fin_period/5 * 3;
		fin_y <= '0';
		wait for fin_period/5;
   end process;
 

   -- Stimulus process
   stim_proc: process
		variable test_rd_clk_iter : integer := 0;
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      --wait for hclk_period*10;

      -- insert stimulus here 
		clr <= '0';
		md <= "11";
		wait for 500 ns;
		md <= "00";
		wait until ready = '1';
		wait for 5ns;
		rd_en <= '1';
		wait for 5ns;
--		while test_rd_clk_iter < 32 loop
--			test_rd_clk_iter := test_rd_clk_iter + 1;
--			rd_clk <= '1';
--			wait for 10 ns;
--			rd_clk <= '0';
--			wait for 10 ns;
--		end loop;
		wait for 725 ns;
		rd_en <= '0';

      wait;
   end process;

END;